1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device and a semiconductor device, and more particularly, to a manufacturing method of a semiconductor device and the semiconductor device with an improved SOI structure.
2. Description of the Related Art
In recent years, large-scaled integrated circuits (chip) wherein a number of elements such as transistors and resistors are connected to constitute an electric circuit, and are integrated on a semiconductor substrate, have frequently been employed in the main portions of a computer or a communicating device. The performance of the device thus depends on the performance of each of the semiconductor devices.
There is also recently proposed a so-called multi-chip semiconductor device using a plurality of chips to improve the performance of the semiconductor device. Some of the multi-chip semiconductor devices are formed to have a plurality of stacked thin chips by employing chip-on-chip technology.
The thin chips are formed with use of the technology called xe2x80x9cback grindingxe2x80x9d. This is a method wherein the rear side face of the wafer is ground with a grinding device after the wafer manufacturing process has finished, to decrease thickness of the wafer.
The thin-chip forming method using the back grinding technique, however, has following problems. That is, it is difficult to make the wafer very thin with the back grinding technique, and thus it takes a long time to attain the very thin wafer. In addition, the grinding process on the rear side face of the wafer physically damages the wafer.
Incidentally, the SOI (Silicon On Insulator) substrate is introduced into the devices used for commercial products to reduce the parasitic capacitance and improve the response of the semiconductor device. On the other hand, multi-layer wiring is employed in semiconductor devices, because the integration density of the devices keeps increasing and the size of their elements keep decreasing. In addition, Cu wires are now used in place of Al wires, because they have lower resistance and higher melting point than Al wires. In view of this, it is expected that the SOI substrate and the Cu wires will be used in combination in order to enhance the integration density and operating efficiency of semiconductor devices.
The Cu wiring has an excellent advantage that the Cu wiring has small RC delay due to the property of the material of the wiring itself and it cannot be easily cut even in the case that the current density is so high (in other words, the Cu wiring has high durability against the electromigration).
Cu, however, has large diffusion coefficient in silicon. Therefore, if the device is subjected to the process with a heat treatment step after the Cu wiring is formed therein, Cu of the Cu wiring is diffused into an interlayer insulating film formed of material belonging to a SiO2 group. The diffusion of Cu into the interlayer insulating film will cause some problems such as the increase of the leak current from the interlayer insulating film and the increase of the dielectric constant. If Cu is diffused into a gate insulation film, the level of the threshold voltage will fluctuate. Cu diffusion will be also caused by a high electric field applied to the Cu.
In order to solve the above-mentioned problems, the side and the bottom surfaces of the Cu wiring are covered with a film called as a barrier metal film made of a metal compound such as TaN that will prevent the diffusion of Cu, and the top surface of the Cu wiring is covered with a so-called top barrier film, i.e., an insulating film such as a silicon nitride film.
The diffusion of Cu into the interlayer insulating film can be prevented in the above-mentioned manner. However, the manner remains a problem in terms of the Cu diffusion.
During the forming process of the Cu wiring, an amount of Cu will adhere to a rear side surface of the silicon substrate. The adhered Cu diffuses into the silicon substrate. If the Cu diffused into the substrate enters into an element region, the deterioration or fluctuation of the characteristics or performance of the elements will occur thereby.
The present invention is intended to provide a semiconductor device manufacturing method which enables shortening the period of time required for preparing a thin substrate (wafer), and to suppressing damage to the thin substrate while preparing the substrate.
The first aspect of the present invention includes a step of preparing an SOI substrate having a supporting substrate, an insulating film formed above the supporting substrate, a semiconductor region formed above the insulating film, and an intermediate layer formed between the supporting substrate and the insulating film, a step of forming a semiconductor element in the semiconductor region, and a step of removing the intermediate layer to separate the supporting substrate and the semiconductor region in which the semiconductor element is formed.
Another object of the present invention is to provide a semiconductor device manufacturing method which is able to prevent metal composing a metal wiring from diffusing from the rear side surface of the semiconductor substrate.
The second aspect of the present invention includes a semiconductor region having a semiconductor element, and a diffusion barrier layer provided in the semiconductor region and shaped like a bowl.
The third aspect of the present invention includes a supporting substrate, an insulating film provided on the supporting substrate, a semiconductor region provided on the insulating film, the semiconductor region having a semiconductor element formed therein, and a diffusion barrier layer a part of which is provided in the semiconductor region, a part of which is provided in the insulating film, a bottom of which is placed in the supporting substrate and shaped like a bowl.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.